1) Field of the Invention
This invention relates generally to devices and methods for the fabrication of semiconductor devices and more particularly to the fabrication of FET's having embedded Source/Drain regions.
2) Description of the Prior Art
It is now well-known that SiGe can be embedded into the S/D regions of PFETs to generate uniaxial stress in the silicon channel. This in turn increases the carrier mobility and thus enhances the PFET device performance significantly. However, the integration of embedded SiGe (eSiGe) into the normal CMOS process flow is extremely challenging. The extent of performance enhancement also depends strongly on the stress generated by the SiGe itself, the active dopant concentration in the eSiGe and the compatibility to stress liners overlying the transistor structures.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 6,861,318: Semiconductor transistor having a stressed channel—Semiconductor transistor for integrated circuits, comprises source and drain formed in source and drain recesses, respectively, source and/or drain being made of film material, which is formed to have second lattice having second spacing Inventor: Murthy, Anand;
U.S. Pat. No. 6,531,347: Method of making recessed source drains to reduce fringing capacitance—Manufacture of semiconductor device involves forming source and drain regions that are recessed at prescribed depth below semiconductor substrate surface Inventor: Huster, Carl
US20050079692A1: Methods to fabricate MOSFET devices using selective deposition process—Fabrication of silicon-based device on substrate surface involves depositing first and second silicon-containing layers by exposing to specified first and second process gases, respectively Inventor: Samoilov, Arkadii V.; Sunn
US20050104057A1: Methods of manufacturing a stressed MOS transistor structure—Manufacture of stressed metal oxide semiconductor transistor structure comprises creating intentionally recessed region in region of semiconductor material, and creating layer on surface of recessed region to induce tensile stress—Inventor: Shaheed, M. Reaz;
US20050136606A1: Spacer for a gate electrode having tensile stress and a method of forming the same—Inventor: Rulke, Hartmut By reducing a deposition rate and maintaining a low bias power in a plasma atmosphere, a spacer layer, for example a silicon nitride layer, may be deposited that exhibits tensile stress. The amount of tensile stress is controllable within a wide range, thereby providing the potential for forming sidewall spacer elements that modify the charge carrier mobility and thus the conductivity of the channel region of a field effect transistor.
U.S. Pat. No. 6,902,971: Transistor sidewall spacer stress modulation—Fabrication of semiconductor, e.g. metal oxide semiconductor transistor, by forming gate electrode on gate dielectric, thermally depositing silicon nitride spacer film, modulating stress characteristic of spacer film, and etching film—Inventor: Grudowski, Paul A.; Austin, Tex., United States of America
US20040142545A1: Semiconductor with tensile strained substrate and method of making the same—Formation of metal oxide semiconductor field effect transistor involves high compression deposition that increases tensile strain in silicon layer—Inventor: Ngo, Minh V.;—shows nitride stress layer over gate.